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Guild: wafer.space Community
Channel: Information / general / gf180mcu_as_sc_mcu7t3v3/example_project ...
After: 10/31/2025 23:59
Before: 12/01/2025 00:00
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[11/26/2025 23:48] bailey8889



[11/26/2025 23:48] bailey8889
@Tholin Sorry, but I don't think my Mac has enough umph to run a design that size. If you get partial logs/reports you can send them to me. 

I've seen long run times when the fill/cap cells aren't parallelized before comparison. May not be relevant.


[11/29/2025 22:12] tholin


{Attachments}
2025-11_media/69-netgen-lvs-ADD1E.zip


[11/29/2025 22:16] bailey8889
Thanks, I'll check later today.


[11/30/2025 12:23] bailey8889
@Tholin the setup file for `gf180mcuD` provides for parallel reduction of `fillcap` cells but not `decap` cells. If you are creating a new standard cell library for `gf180mcu_as_sc_mcu7t3v3` then I suggest you either,
1. rename the `decap` cells to `fillcap` to match the `5v0` libraries or
2. modify the netgen setup file to reduce parallel `decap` cells.


[11/30/2025 17:26] tholin
I did this and its still taking forever. There are also still warnings in the log that I don”t see with the 5V SCL


[11/30/2025 17:27] tholin


{Attachments}
2025-11_media/image-FD25E.png
2025-11_media/image-65112.png


[11/30/2025 20:58] bailey8889
The first is due to yosys adding buffers to increase capacitance on nets (I think). The outputs are unconnected - normal.
The second is netgen output saying that it was told to ignore a parameter that did not exist on a device - also normal.

If you could send me the partial log, I can take a look at it.


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